1. Field of the Invention
The present invention relates to a program-developing emulator microcomputer and piggyback microcomputer which are used in, for example, development of microcomputer applications, as well as to a level converter circuit which is incorporated in such a microcomputer. The invention also is concerned with an LSI test system and an emulator system which use the above-mentioned microcomputers.
2. Description of the Related Art
There is a current trend towards reduction in the source voltages for various integrated circuit devices to cope with demands for reduction in electrical power consumption and adaptability to battery power supply. For instance, a microcomputer unit which can operate with a single battery (D.C. 1.5 V) has been brought to market. In general, a microcomputer incorporates programs. In order to develop such programs, it is necessary to develop also an emulator microcomputer or a piggyback microcomputer separately from the mass-produced microcomputers as the commercial goods.
EPROMs loaded on a piggyback microcomputer or an emulator for operating the emulator microcomputer usually require a source voltage of 5 V. It is therefore necessary to employ a level converter circuit for converting the source voltage when the EPROM is connected to a microcomputer which operates with a voltage lower than the source voltage for the EPROM.
A description will now be given of the level converter circuit. Problems encountered when the level converter circuit is not used will be described first, with specific reference to FIG. 19.
FIG. 19 is a circuit diagram of a complementary MOS integrated circuit. N-channel MOSFETs 122 and 124 have sources connected to a negative electrode which is kept at 0 (zero) potential. A P-channel MOSFET 121 has a source connected to a first positive electrode which is held at a potential El, while a P-channel MOSFET 123 has a source connected to a second positive electrode which is held at a potential E2. A relationship E1&lt;E2 exists for these potentials E1 and E2.
An input signal 125 is inverted into an inverted input signal 126 through an inverter circuit which is constituted by the MOSFETs 121 and 122. The inverted input signal 126 is supplied to the gate of an inverter circuit which is constituted by the MOSFETs 123 and 124. In the described circuitry, a potential between 0 and E2 appears at the output terminal 127. In order that the potential 0 is obtained at the output terminal 27, it is necessary to turn off the MOSFET 123 while turning on the MOSFET 124. Therefore, in order to achieve stable operation, it is preferred that the level of the inverted input signal 126 be high. Actually, however, the level of this signal is limited to the range only between 0 and E1. The MOSFET 123 cannot be turned off even when the inverted input signal 126 is set to the highest level, i.e., E1, if the MOSFET 123 has such a threshold level V.sub.TH that meets the condition of E2-E1&gt;V.sub.TH. This not only makes it impossible to set the level of the output terminal 127 to 0 but undesirably allows a current to flow from the second positive electrode of the potential E2 to the negative electrode of the 0 potential through the MOSFETs 123 and 124. Consequently, the expected operation is not always ensured, and low current consumption, which is one of the advantages of complementary MOS integrated circuit, is greatly impaired.
The level converter circuit is used to eliminate the problem described above. FIG. 20 illustrates the most basic complementary level conversion circuit which uses P-channel MOSFETs and N-channel MOSFETs.
Referring to FIG. 20, sources of N-channel MOSFETs 21, 23 and 25 are connected to the negative voltage of 0 potential. The source of a P-channel MOSFET 20 is connected to a first positive electrode of a potential El. Sources of P-channel MOSFETs 22 and 24 are connected to a second positive electrode of potential E2. A signal is input through a terminal 207 so that an inverted signal 202 is obtained. The levels of the signals 201 and 202 vary between 0 and El. The level converter circuit produces an output signal 203. A signal 204 is obtained through inversion of the signal 203.
The level of the signals 203 and 204 vary between 0 and E2. When the signal 201 is 0 potential (low level), the signal 202 takes the potential E1, while the signal 203 takes the 0 potential and the signal 204 is set to the potential E2, whereby the MOSFETs 20, 22 and 25 are turned on, while the MOSFETs 21, 23 and 24 are turned off. Conversely, when the signal 201 is set to the potential E1 (high level), MOSFET 23 is turned on to change the level of the signal 204 towards 0. At the same time, the level of the signal 202 is set to 0, thus turning off the MOSFET 25.
Consequently, MOSFETs 25 and 23 are turned off and on, respectively, so that the MOSFET 22 is urged towards off state, while MOSFET 24 is urged towards on state. Consequently, the levels of the signals 203 and 204 respectively tend toward E2 and 0, thus accelerating the switching tendencies of MOSFET 22 and MOSFET 24 towards off and on states, respectively. Finally, a balance or equilibrium state is obtained in which the signals 201, 202, 203 and 204 are respectively set to potentials E1, 0, E2 and 0, with MOSFETs 20, 22 and 25 turned off and MOSFETs 21, 23 and 24 turned on, respectively.
When the signal 201 is set again to potential 0, MOSFET 23 is turned off so that the signal 202 is turned to the potential E1, thus turning MOSFET 25 on. Consequently, the level of the signal 203 tends to vary towards 0. Since MOSFET 23 is off while MOSFET 25 is on, MOSFET 22 is urged towards on while MOSFET 24 is urged towards off, causing the signals 203 and 204 to vary towards the potential 0 and the potential E2, respectively. Consequently, MOSFETs 24 and 24 are respectively accelerated towards on and off states, respectively, finally establishing an equilibrium state in which the levels of the signals 201, 202, 203 and 204 are respectively set to 0, E1, 0 and E2, with MOSFETs 20, 22 and 25 and MOSFETs 21, 23 and 24 turned to on and off states, respectively.
The above-described circuit operation can be performed smoothly by virtue of the fact that the gate control for N-channel MOSFETs 21, 23 and 25 having source potential of 0 is conducted within the range of potential between 0 and E1, that the gate control of P-channel MOSFET 20 having the source potential E1 is conducted within the range of potential between 0 and E1 and that the gate control for P-channel MOSFETs 22 and 24 having the source potential E2 is conducted within the range of potential between 0 and E2. In particular, the safer operation of the circuit shown in FIG. 20 than that of the circuit shown in FIG. 19 due to the fact that the gate voltages of MOSFETs 22 and 24 are controlled within the range of potential between 0 and E2, i.e., the fact that each of these MOSFETs is supplied with a gate voltage which is high enough to turn each MOSFET on or off.
A description will now be given of a conventional emulator microcomputer and an emulator system. FIG. 21 shows the circuit of emulator system which does not use any level converter circuit.
Referring to FIG. 21, numeral 141 denotes an emulator microcomputer, 142 denotes an emulator which controls the emulator microcomputer 141, and 143 denotes a target system for realizing a desired function by applying a microcomputer. The target system 143 is so constructed that terminals of the emulator microcomputer 141 are connectable thereto. After completion of debugging by the emulator system, a piggyback microcomputer or a mass-produced microcomputer as commercial goods can be connected to the target system 143 in place of the emulator microcomputer 141. A connection interface 144 is provided in the emulator 142 to enable connection of the emulator microcomputer 141. Numeral 1401 denotes a power supply of, for example, 5 volts. A signal line 1402, which is necessary for the emulator 142 to operate the emulator microcomputer 141, includes various lines such as an address signal line, a data signal line and a control BUS. Numeral 1403 denotes a signal line through which the target system 143 and the emulator microcomputer 141 are connected to each other.
The operation of the described system is as follows. A program for the operation of the emulator microcomputer 141 is incorporated in the emulator 142. The delivery of this program, as well as receipt of data from the microcomputer 141, is conducted via the signal line 1402. As the microcomputer 141 is operated, the target system 143 is activated in accordance with signals delivered through the terminals of the microcomputer 141. Signals such as those delivered through the terminals of the microcomputer 141, power supply clocks required for the operation of the microcomputer 141, reset signals, and so forth are supplied from the target system 143 to the microcomputer 141 via a signal line 1403. The emulator 142 is provided with debugging function and is capable of easily altering programs and conforming operations. The program to be installed on the mass-produced microcomputer is fabricated after debugging performed by the emulator 142. FIG. 22 illustrates an image of the described emulate system using the emulator microcomputer. An emulator microcomputer 153 is connected to the main part 151 of the emulator through a pod circuit 152. The emulator microcomputer 153 is connected to the target system 154 through, for example, an IC socket provided on the target system 154.
The use of the piggyback microcomputer is as follows. The program after debugging is written in EPROM. Using this EPROM, a final check of operation of the target system 143 is conducted by the piggyback microcomputer. FIG. 23 illustrates an image of the piggyback microcomputer. EPROM 162 storing the program written therein is connected to a piggyback microcomputer 161 and, in this state, the piggyback microcomputer 161 is connected to the target system.
FIG. 24 is a diagrammatic illustration of an emulator system which is used when the emulator 142 operates with a source voltage of 5 volts while the emulator microcomputer 141 and the target system 143 operate with a source voltage of 3 volts. A level converter circuit 145 is incorporated in the emulator 142. The level converter circuit 145 is formed of ICs which are presently available easily. The power supply of 3 volts is designated at a numeral 1404.
The emulator 142 operates with a source voltage of 5 volts. Therefore, the level converter circuit 145 added to the connector interface 144 converts the level of the signal line 141 to 3 volts to enable exchange of signals between the emulator 142 and the emulator microcomputer 141. Since emulator microcomputer 141 operates with a source voltage of 3 volts, the signal level of the signal line 1403 also is set to 3 volts, so that the target system 143 also operates with the source voltage of 3 volts. Even if the target system 143 designed for operation with a source voltage of 3 volts is operable with a voltage of 5 volts, any analog circuit or circuits which may exist in the target system preferably operate with the design source voltage of 3 volts, because such analog circuit or circuits have a large voltage-dependency. It is also necessary that the operation voltage be held at 3 volts during debugging, in order that evaluation and debugging are conducted by the emulation system under conditions which approximate, as much as possible, the actual conditions.
The level converter circuit of the type shown in FIG. 20 is incorporated in a part of an ordinary IC. It is impossible to obtain a level converter circuit alone. Practically, therefore, the level converter circuit 145 is constructed with circuits as shown in FIGS. 25 and 26. In these Figures, numeral 191 designates an open-collector inverter such as LSO 5, 192 denotes an inverter such as a circuit LSO 4, 1901 designates a power supply of 5 volts, 1902 denotes a power supply of 3 volts, 1903 and 1905 denote signal lines carrying signals of a level of 5 volts, 1904 and 1906 denote signal lines carrying signals of a level of 3 volts, and 193 and 194 denote pull-up resistors. The operation of the level converter circuit is illustrated in a timing chart in FIG. 27. The inverter circuit LSO 5 shown in FIG. 25 cannot produce a high level so that the level is pulled down to 3 volts by means of the pull-up resistor 193. On the other hand, the inverter circuit LSO 4 shown in FIG. 26 is capable of receiving signals of 3 volts even when the power supply voltage is 5 volts, because the voltages V.sub.1H and V.sub.1L are respectively 2 volts and 0.8 volts. However, since the output voltage V.sub.OH is 2.7 volts, the pull-up resistor 194 is used to pull up the output level to 5 volts. Thus, the circuit shown in FIG. 25 is capable of converting the input voltage of 5 volt to a voltage ranging between 2 and 7 volts, whereas the circuit shown in FIG. 26 is capable of converting an input voltage of 2 to 7 volts into an output voltage of 5 volts.
It is to be understood, however, that neither the circuit shown in FIG. 25 nor the circuit shown in FIG. 26 is able to produce a conversion output of 2 volts or lower. Furthermore, with these circuits, it is not easy to effect the level conversion particularly when the signal frequency is high, due to problems such as a rise of the output low level above 0 volts or distortion of waveform during conversion from low to high levels due to the use of the pull-up resistors 193 and 194. In addition, large electric currents are consumed in these circuits.
The level converter circuit of the type shown in FIG. 20 can safely operate despite any slight reduction of the potential E1 of the first positive electrode, but is not prepared for any reduction in the potential E2 of the second positive electrode. Thus, the level converter circuit of this type may fail to operate correctly when the potential E2 of the second positive electrode has been lowered. Namely, in such a case, it is difficult to convert an input voltage of 5 volts into an output voltage of 1 volt as shown in FIG. 28. In order to ensure safe functioning of the level converter circuit despite any reduction of the potential E2 of the second positive electrode, it is necessary that the P-channel MOSFETs 22 and 24 be designed to have sufficiently large .beta. values.
It will not be so often required to vary the source voltage of the target system to a value ranging between 2 volts and 11 volts by the operation of the emulator system. Such a control, however, is needed when the emulator microcomputer is used for the purpose of testing mass-produced microcomputers.
FIG. 29 illustrates the construction of an LSI test system which uses an emulator microcomputer. The LSI test system includes the following parts or components: an LSI tester 161 for controlling the whole system; a device under test (DUT) 162 such as a microcomputer to be tested; an interface board 163 for interconnecting the LSI tester 161 and the DUT 162; a microcomputer 164 which is an emulator microcomputer or a piggyback microcomputer; a level converter circuit 165 similar to the level converter circuit 145 shown in FIG. 24; serial I/O ports 166, 169 used for serial communication; a memory 167 storing a program for operating the emulator microcomputer 164; an interface 168 for signal exchange between the emulator microcomputer 164 and the LSI tester 161; a 5-volt power supply 1601 derived from the LSI tester 161; a power supply 1602 supplied from the LSI tester 161 and used in testing the DUT 162; a signal line 1603 for exchange of signals between the LSI tester 161 and the interface board 163; a signal line 1604 for signal exchange between the DUT 162 and the level conversion circuit 165; a BUS 1605 which interconnects the emulator microcomputer 164 to the memory 167 and the interface 168; and a signal line 1606 for interconnecting the emulator microcomputer 164 and the level converter circuit 165.
The DUT 162, if it is an ordinary microcomputer, is constructed such that its address BUS and data BUS are externally connectable through terminals. It is therefore possible to test the DUT 162 by directly connecting it to the LSI tester 161. In the case of a microcomputer of the type which has only one serial I/O terminal, as is the case of an IC card microcomputer, it is necessary that all the tests be executed through this serial I/O. According to a testing method which is currently used for testing IC card microcomputers, a test program is introduced into the memory of the PUT through the serial I/O so that the PUT itself executes the test program and delivers the results of the test through the serial I/O. When this method is carried out through direct connection between the LSI tester and the DUT, an enormous number of test programs have to be delivered to the microcomputer as the DUT, which excessively burdens the LSI tester.
As a measure for solving this problem, it has been practiced to load an emulator microcomputer 164 on an interface board 163 such that the emulator microcomputer executes the serial data exchange with the DUT 162, thus unburdening the LSI tester 161. The memory 167 stores a program which is necessary for operating the serial I/O 166 and the interface 168 of the emulator microcomputer 164.
In general, testing of a microcomputer as the DUT 162 has to be done at various levels of the power supply voltage. Thus, the level of the signals on the signal line is varied, so that conversion of the level has to be done between the signal line 1604 and the signal line 1606. The level converter circuit 165 is provided to meet such a demand.
In this level converter circuit 165, however, the signal level is variable only over a limited range because this level converter circuit 165 has a construction similar to the circuit 145 shown in FIG. 24.
Conventional piggyback microcomputers are not adaptable to target systems operable with 3-volt power, because such microcomputers have EPROMs designed to operate with the power of 5 volts. Although EPROMs operable with a power supply at 3 volts have been commercially produced in recent years, piggyback microcomputers using such EPROM cannot be satisfactorily used when the target system operates with a source voltage of 3 volts or lower.
As will be understood from the foregoing description, the conventional emulator microcomputer and piggyback microcomputer require external provision of a level converter circuit when the operation voltage of the target system is different from that of the emulator. It has therefore been necessary to modify the emulator or the pod circuit in accordance with the type of the microcomputer of the target system or the source voltage of the target system. In addition, a conventional level converter circuit could not satisfactorily be used for an emulator system of the kind described, because it cannot perform level conversion to a low level, e.g., 2 volts or lower.